Phase locked loop circuits (PLL) are used to generate an output signal that has the same phase as a reference signal. Typically, PLLs include a phase/frequency detector, a charge pump, loop filter, and a controlled oscillator. The charge pump provides the output signal(s) that control the oscillator.
FIG. 1 illustrates a conventional single ended charge pump 10 that may be used in a PLL, along with a phase/frequency detector (PFD) 12. Charge pump 10 includes transistors 14 and 16, which may be, e.g., n-channel transistors, coupled in series between current sources 18 and 19. The PFD 12 receives and compares the frequency of a reference clock signal (Fin) with a feedback clock signal (Fclk). The PFD 12 provides an up voltage signal to transistor 14 and a down (dn) voltage signal to transistor 16. The output terminal of the charge pump 10 is between transistors 14 and 16 and provides a control voltage Vop to a voltage controlled oscillator (not shown). A loop filter 20 is disposed between the charge pump 10 and the voltage controlled oscillator.
Timing diagrams for the single-ended charge pump 10 are illustrated in FIGS. 2A and 2B. In operation, PFD 12 compares the frequency of a reference clock signal (Fin) with the feedback clock signal (Fclk). If the phase or frequency of the feedback clock Fclk is delayed compared to the reference clock frequency Fin, the PFD 12 generates an up signal, as illustrated in FIG. 2A, and a low down signal. The up signal is received by transistor 14 and the low down signal is received by transistor 16. Thus, the current source 16 will charge the loop filter 20, which will increases the VCO control voltage Vop.
If the phase or frequency of the feedback clock Fclk leads the reference clock Fin, the PFD 12 generates a down (dn) signal, as illustrated in FIG. 2B and a low up signal. The dn signal is received by transistor 16 and the up signal is received by transistor 14. Thus, the loop filter 20 will discharge via transistor 16, which will decrease the control voltage Vop. When Fin and Fclk are in phase with a same frequency, the up and dn signal have the same minimum pulse width to avoid a dead zone, which improves the linearity of the charge-pump characteristic curve while avoiding changing the control voltage Vop.
FIG. 3 illustrates a conventional fully differential charge-pump circuit 50 with a common-mode dc feedback. Charge pump 50 includes four pairs of differential n channel transistors 55 and 56, 57 and 58, 59 and 60, and 61 and 62. Each differential pair of transistors receives differential signals (up, /up, and dn, /dn) from the phase/frequency detector in the PLL. Thus, for example, transistors 55 and 56 receive the up voltage signal and the up bar (/up) signal, respectively, as do transistors 61 and 62. Similarly, transistors 57 and 58 receive the down (dn) and the down bar (/dn) signals, respectively, as do transistors 59 and 60.
Transistors 55 and 57 are coupled in series, as are transistors 56 and 58, between current sources 52 and 54, and an output terminal is disposed between transistors 55 and 57. A loop filter 18a is coupled to the output terminal between transistors 55 and 57, which produces a control voltage Vop. An op-amp 59 is also disposed between current sources 52, 54, with the non-inverting input terminal coupled to the output terminal disposed between transistors 55 and 57 and the output terminal of the op-amp 59 is coupled between transistors 56 and 58 and is coupled to the inverting input terminal to form a negative feedback loop.
Similarly, transistors 59 and 61 are coupled in series, as are transistors 60 and 62, between current sources 62 and 64 and an output terminal is disposed between transistors 59 and 61. A second loop filter 18b is coupled to the output terminal between transistors 59 and 61, which produces a control voltage Von. A second op-amp 69 is disposed between series coupled transistors 59, 61 and 60, 62 similar to the configuration of op-amp 59 described above.
A trans-conductance amplifier 70 is coupled to the output terminals of the charge pump 50 and provides the dc common mode feedback. The amplifier 70 provides negative feedback as the common center voltage of the differential output, Vop and Von, based on the reference voltage Vr, which is normally Vdd/2.
The op-amps 59 and 69 reduce the transients caused by the charge transfer as the charge pump current is switched. By way of example, when nodes N1 and N2 are not switched to Vop they are biased by the op-amp 59 that operates as a negative feedback unit-gain amplifier. In addition, the op-amp 59 suppresses any charge sharing from the parasitic capacitance on nodes N1 or N2 that can cause mismatch between the up and down current sources 52, 54.
Unfortunately, the negative feedback unity gain amplifiers 59 and 69 are difficult to design with a low power supply, which is the trend in current technology. Further, the op-amps 59, 69 require a large layout size. Thus, what is needed is an improved charge-pump circuit, e.g., that does not require a large layout and that can operate with a low power supply.